Field of the Invention
The invention relates to an SRAM cell configuration in which a memory cell comprises at least six transistors, and also to a method for its fabrication.
An SRAM cell configuration is a memory cell configuration with random access to stored information. In contrast to a DRAM cell configuration, in which the information has to be refreshed at regular intervals, the information in an SRAM cell is stored statically.
In SRAM cell configurations, use is increasingly being made of so-called 6 T memory cells, that is to say memory cells having six transistors. A 6 T memory cell comprises four MOS transistors interconnected as flip-flop and two selection transistors. The flip-flop is in one of two stable states. The state of the flip-flop represents a logic value, 0 or 1. By driving the selection transistors via a word line, it is possible, via two bit lines, both to determine the state and thus to read out the information and also to change the state and thus store a new item of information.
Since the storage density increases from memory generation to memory generation, it is necessary to reduce the required area of the 6 T memory cell from generation to generation.
A 6 T memory cell that can be fabricated with an area of 55F.sup.2 (F is the minimum structure size that can be fabricated using the respective technology), is presented in Semiconductor International (Nov. 1996), pages 19 and 20. Use is made of self-aligned, i.e. fabricated without the use of masks to be aligned, contacts and also local connections, i.e. connections situated within the cell.